S-R

Definition

An S-R latch is a basic sequential logic circuit with two inputs, S (Set) and R (Reset), and two outputs, usually Q and Q̅. It is used to store one bit of data. The Set input makes the output Q become 1, and the Reset input makes Q become 0. The latch retains its last state when neither input is active.

Depending on how it is built, the S-R latch may be implemented using:

NOR gates

with active-high inputs

NAND gates

with active-low inputs

It is called a latch because it “latches” onto a state and holds it until directed to change.

Main Content

1. S-R Latch Structure

The S-R latch is formed by cross-coupling two logic gates so that each output feeds back into the other gate’s input.
This feedback creates memory, allowing the circuit to store a single binary value.

A basic NOR-based S-R latch can be shown as:

      S ───┐         ┌───── Q
           │   NOR   │
           ├────────▶│
           │         └───┬─
           │             │
           │             │
           │         ┌───┴─
           └────────▶│   NOR   ├──── Q̅
      R ───┐         │         │
           └────────▶└─────────┘

A more standard representation is:

         ┌───────┐            ┌───────┐
   S ───▶│  NOR  │─── Q ──────▶│  NOR  │─── Q̅
         └───────┘            └───────┘
             ▲                     ▲
             └──────── Q̅ ─────────┘
                   R input

Key structural points:

The two outputs are complementary in normal operation: if Q = 1, then Q̅ = 0, and vice versa.
The feedback path is what gives the latch its memory behavior.
The circuit does not require a clock, so it is an asynchronous storage device.

2. S-R Latch Operation

The latch responds to the S and R inputs by changing or preserving its state.
There are four possible input combinations, but not all are valid or useful.

For a NOR-based S-R latch:

S = 1, R = 0

→ Set state, Q = 1

S = 0, R = 1

→ Reset state, Q = 0

S = 0, R = 0

→ Hold state, output remains unchanged

S = 1, R = 1

→ Invalid/forbidden condition

Truth table for NOR-based S-R latch:

S	R	Q(next)	Q̅(next)	Meaning
0	0	Q(prev)	Q̅(prev)	Hold
0	1	0	1	Reset
1	0	1	0	Set
1	1	Invalid	Invalid	Not allowed

Important behavior:

In the hold condition, the latch keeps the previously stored bit.
In the invalid condition, both outputs may temporarily become 0, breaking the complementary relationship and causing uncertainty when inputs return to normal.

For a NAND-based S-R latch:

Inputs are active low
The active conditions are reversed compared with NOR implementation:
S = 0 sets the latch
R = 0 resets the latch
S = 1, R = 1 holds state
S = 0, R = 0 is invalid

This difference is essential in digital design because the same logic function can be implemented with different gate types and active levels.

3. S-R Latch Characteristics and Invalid State

The S-R latch is a level-sensitive memory element, not edge-triggered.
It can change state as long as the active input level is present.
It is very useful, but it has an important limitation: the forbidden state.

Why the invalid state is problematic:

In the NOR latch, applying S = 1 and R = 1 forces both outputs low.
When the inputs return to 0 simultaneously, the final stored state may depend on tiny gate delays.
This can lead to metastability or unpredictable output behavior.

Metastability means:

The circuit may temporarily settle in an undefined intermediate condition.
It may take an unpredictable time to reach a stable 0 or 1.
This is dangerous in synchronous digital systems because it can cause logic errors.

Example:

Suppose an S-R latch controls a memory bit.
If both set and reset are asserted at once due to faulty control logic, the bit may not have a clear stored value.
Proper system design avoids this by ensuring mutually exclusive control signals.

Common practical uses of this concept:

As a simple memory cell
In switch debouncing circuits
As the basis for more advanced flip-flop designs
In control logic where a state must be remembered

Working / Process

1. Apply an input condition

If the Set input becomes active, the latch is driven toward storing a 1.
If the Reset input becomes active, the latch is driven toward storing a 0.
If neither input is active, the latch remains in its current state.

2. Feedback updates the outputs

The output from one gate is fed back into the other gate.
This feedback reinforces one stable state and suppresses the opposite state.
The circuit settles quickly into a stable memory condition.

3. Store and maintain the value

Once the desired state is reached, the inputs can return to inactive.
The latch continues to hold the last state because of the feedback loop.
It will remain unchanged until a new Set or Reset command is given.

Example of operation in a NOR latch:

Start with Q = 0, Q̅ = 1
Apply S = 1, R = 0
Output changes to Q = 1, Q̅ = 0
Return S to 0
The latch still keeps Q = 1, showing memory

Advantages / Applications

Simple memory storage

Stores one bit of data using only a few logic gates.

Fundamental building block

Used as the basis for flip-flops, registers, and more complex sequential circuits.

Useful in control systems

Applied in switch debouncing, alarms, latching relays, and basic state-control circuits.

Additional practical value:

It helps learners understand the concept of feedback in digital electronics.
It demonstrates how digital circuits can “remember” information without continuous input.
It is an important step toward understanding synchronous memory elements and timing-controlled logic.

Summary

The S-R latch is a simple circuit that stores one bit using Set and Reset inputs.
It works through feedback and has two stable states.
It has a hold condition and an invalid condition that must be avoided.
Important terms to remember: Set, Reset, latch, feedback, bistable, hold state, invalid state, metastability