2732 etc. & Their Address Decoding. Modern Trends in Semiconductor Memories such as DRAM

Definition

Address decoding is the process of using the higher-order address lines of a microprocessor or microcontroller to select a specific memory chip or memory block from among many possible devices in a memory map.

A 2732 EPROM is a non-volatile memory chip with a storage capacity of 4 kilobytes (4096 bytes) organized as 4 K × 8, meaning it contains 4096 memory locations and each location stores 8 bits (1 byte).

DRAM (Dynamic Random Access Memory) is a volatile semiconductor memory that stores each bit in a capacitor and requires periodic refreshing to retain data.

Main Content

1. 2732 EPROM and Memory Organization

• The 2732 EPROM is an older but very important memory device used to understand basic memory organization. It stores 4 K bytes, and since each location is 8 bits wide, it is called 4 K × 8 memory.
• It typically uses 12 address lines because $2^{12} = 4096$, allowing the chip to uniquely access all 4096 locations. The address lines are usually named A0 to A11, while the data lines are D0 to D7.
• Since it is an EPROM (Erasable Programmable Read-Only Memory), it can be programmed electrically and erased using ultraviolet light, making it reprogrammable but non-volatile.
• In system design, the 2732 is often mapped into a larger address space by using address decoding. The CPU may generate more address bits than the chip needs, so the unused upper-order lines are decoded to enable the chip only in its assigned memory region.
• Example: If a microprocessor has a 16-bit address bus, it can address 64 KB memory space. A 2732 needs only 4 KB, so it can be placed at any 4 KB boundary such as 0000H–0FFFH, 1000H–1FFFH, etc.

2. Address Decoding Techniques

Address decoding

• ensures that only one selected memory chip responds when the CPU accesses a given address. Without decoding, multiple chips might respond simultaneously, causing data bus conflicts and incorrect memory access.
• There are two main forms:
• Absolute decoding
• Partial decoding
• In absolute decoding, all higher-order address lines are decoded so that only one unique memory chip is selected for a particular address range. This is the most reliable and correct method.
• In partial decoding, not all higher-order address bits are used. This simplifies hardware but can create memory mirroring or aliasing, where the same memory chip appears at multiple address locations.
• Decoding is implemented using logic gates, NAND/NOR gates, or decoder ICs such as 74LS138. For example, a 3-to-8 decoder can decode three address lines into eight chip-select outputs.
• Example: To map a 2732 EPROM into 0000H–0FFFH, the upper address lines must be fixed to the binary pattern corresponding to that block, while A0–A11 go directly to the EPROM and the rest are decoded using logic.

3. Modern Semiconductor Memory Trends and DRAM

• Modern memory systems focus on high density, low cost, high bandwidth, and low power consumption. DRAM is the most widely used main memory because it offers much higher storage capacity than SRAM at a lower cost.
• In DRAM, each bit is stored as charge in a tiny capacitor and accessed through a transistor. Because capacitors leak charge over time, DRAM cells must be refreshed periodically.
• The major trend in DRAM technology has been increasing density by reducing transistor and capacitor sizes using advanced fabrication processes. This has led to memory chips with gigabytes of capacity in tiny packages.
• Modern DRAM types include:
• SDRAM (Synchronous DRAM)
• DDR SDRAM
• DDR2, DDR3, DDR4, DDR5
• LPDDR for mobile and low-power devices
• GDDR for graphics applications
• Key modern trends include:
• Burst transfer modes for higher throughput
• Double data rate operation to transfer data on both clock edges
• Prefetch architectures to improve speed
• Low-voltage operation for reduced power
• Stacked and multi-chip modules for compact high-capacity systems
• DRAM contrast with EPROM/ROM:
• EPROM is non-volatile and stores firmware
• DRAM is volatile and stores working data temporarily
• EPROM uses address decoding for chip selection in memory maps
• DRAM uses row/column multiplexing and refresh control for efficient large-scale storage

Working / Process

1. Memory Address Generation

• The CPU generates a binary address for the desired memory location.
• For a 2732 EPROM, only 12 address bits are needed internally, but the full system address may contain more bits.
• The higher-order bits determine which memory chip is selected.

2. Address Decoding and Chip Selection

• External logic decodes the upper address lines to produce a chip select signal.
• If the address falls within the assigned memory range, the decoder enables the 2732 EPROM or another memory device.
• The selected memory chip places the requested byte on the data bus.

3. Read / Refresh / Access Operation

• In a read cycle, the address is applied, the chip is enabled, and the data is output.
• In DRAM, after reading or writing, the memory controller schedules refresh cycles to restore charge in the capacitors.
• A modern DRAM access typically uses row address strobe (RAS) and column address strobe (CAS) operations, where the address is multiplexed to reduce pin count.

Example of Address Decoding for 2732

Suppose a 2732 EPROM is mapped from 0000H to 0FFFH in a 16-bit address space.

• Memory size of 2732 = 4 KB = 2^12 bytes
• Therefore, A0–A11 connect directly to the EPROM address pins
• Upper address lines A12–A15 must be fixed at 0000 for the first 4 KB block

Address range table

Simple chip-select idea

A15 A14 A13 A12  ---> Decoder --->  Chip Select for 2732
 0   0   0   0    --->  Enable  --->  2732 active

Block-level connection

CPU Address Bus
A0-A11 -----------------------> 2732 Address Inputs
A12-A15 -----> Decoder -------> Chip Select

CPU Data Bus
D0-D7 <-----------------------> 2732 Data Lines

DRAM Working Illustration

CPU Address --> Memory Controller --> Row Address
                                  --> Column Address
                                         |
                                         v
                                   DRAM Cell Array
                                         |
                                   Data I/O + Refresh

Advantages / Applications

2732 EPROM and decoded memory systems

• are very useful in learning memory interfacing, address mapping, and chip-select generation in microprocessor-based systems.

EPROMs

• are ideal for storing fixed program code such as firmware, boot loaders, and embedded control programs because they are non-volatile and retain data without power.

DRAM

• is the primary memory technology used in desktops, laptops, servers, and mobile devices due to its high density and low cost per bit.
• Address decoding allows a processor to manage multiple memory chips efficiently, enabling expansion of memory capacity and organized memory maps.
• Modern DRAM technologies support high-performance computing, graphics processing, artificial intelligence workloads, and large-scale data systems.

Summary

• The 2732 EPROM is a 4 K × 8 non-volatile memory chip used to understand memory organization and address mapping.
• Address decoding selects the correct memory chip by interpreting higher-order address bits.
• DRAM is the dominant modern semiconductor memory because it offers high density, low cost, and large capacity.
• Important terms to remember: 2732 EPROM, 4 K × 8, address decoding, chip select, absolute decoding, partial decoding, DRAM, refresh, RAS, CAS, DDR